Modern computing devices, such as mobile phones, may have substantial energy consumption restrictions due to battery life and overheating concerns. While dynamic random access memory (DRAM) structures within such devices may provide relatively good read/write performance, DRAM standby power may be relatively high. Non-volatile random access memory (NVRAM) structures, on the other hand, may have lower standby power than DRAM structures, but NVRAM write performance may be relatively poor. Recent developments in computing device design may employ a hybrid memory architecture that includes a small amount of DRAM and a larger amount of NVRAM, wherein specialized hardware may attempt to store heavily written data in the DRAM and store rarely accessed data in the NVRAM. For example, the specialized hardware might include a memory management unit (MMU) that observes address traffic at the processor instruction level in order to distinguish between heavily written data and rarely accessed data. Such a hardware based approach may increase cost, risk and time to market (TTM).